1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device having a power-on reset circuit.
Priority is claimed on Japanese Patent Application No. 2009-023907, filed Feb. 4, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Japanese Unexamined Patent Application, First Publication, No. JP-A-5-119871 discloses a semiconductor device which has a power voltage level detection circuit (or a power-on reset circuit). The power voltage level detection circuit resets a predetermined circuit block in the semiconductor device when the power voltage level varies or fluctuates, for example, when power on and power off. The power-on reset circuit monitors variation or fluctuation in the power voltage level and activates a power-on reset signal to initialize (reset) a predetermined circuit block until the power voltage level is increased up to a power-on determination voltage after a predetermined time is elapsed from the startup of the power voltage level when the power voltage starts to be supplied.
Additionally, the power-on reset circuit activates the power-on reset signal again when the power voltage level supplied to such a predetermined circuit block is reduced under the power-on determination voltage even after the power voltage level is stabilized, i.e., when the power voltage is suddenly discontinued to be supplied.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2005-347862 discloses a voltage converter circuit which converts the amplitude of a predetermined internal signal of the semiconductor device unlike the power-on reset circuit.